Description

Revision Standard – Active – Draft.Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, the means by which EDA vendors can meet their application performance and capacity needs are discussed.

Product Details

ISBN(s):

9781504461610

Number of Pages:

658

File Size:

1 file , 10 MB

Product Code(s):

STDAPE23887